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authorEddie Hung <eddie@fpgeh.com>2020-04-02 11:47:25 -0700
committerGitHub <noreply@github.com>2020-04-02 11:47:25 -0700
commit5f662b1c43052bf48558be12ff0013f2e39ae9ab (patch)
tree2e0bb8da3b23cc1bfac332115502759223afea52 /passes/cmds/splice.cc
parent0ed1062557ac9c7fd3d930ffc75f6df9424a87cd (diff)
parent956ecd48f71417b514c194a833a49238049e00b0 (diff)
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Merge pull request #1767 from YosysHQ/eddie/idstrings
IdString: use more ID::*, make them easier to use, speed up IdString::in()
Diffstat (limited to 'passes/cmds/splice.cc')
-rw-r--r--passes/cmds/splice.cc28
1 files changed, 14 insertions, 14 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index bafafca4e..f99090279 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -75,13 +75,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice");
- cell->parameters["\\OFFSET"] = offset;
- cell->parameters["\\A_WIDTH"] = sig_a.size();
- cell->parameters["\\Y_WIDTH"] = sig.size();
- cell->setPort("\\A", sig_a);
- cell->setPort("\\Y", module->addWire(NEW_ID, sig.size()));
- new_sig = cell->getPort("\\Y");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
+ cell->parameters[ID::OFFSET] = offset;
+ cell->parameters[ID::A_WIDTH] = sig_a.size();
+ cell->parameters[ID::Y_WIDTH] = sig.size();
+ cell->setPort(ID::A, sig_a);
+ cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
+ new_sig = cell->getPort(ID::Y);
}
sliced_signals_cache[sig] = new_sig;
@@ -132,13 +132,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
- cell->parameters["\\A_WIDTH"] = new_sig.size();
- cell->parameters["\\B_WIDTH"] = sig2.size();
- cell->setPort("\\A", new_sig);
- cell->setPort("\\B", sig2);
- cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
- new_sig = cell->getPort("\\Y");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
+ cell->parameters[ID::A_WIDTH] = new_sig.size();
+ cell->parameters[ID::B_WIDTH] = sig2.size();
+ cell->setPort(ID::A, new_sig);
+ cell->setPort(ID::B, sig2);
+ cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
+ new_sig = cell->getPort(ID::Y);
}
spliced_signals_cache[sig] = new_sig;