diff options
| author | whitequark <whitequark@whitequark.org> | 2020-06-10 14:39:45 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-10 14:39:45 +0000 |
| commit | 0955a603c889e3ce86ca65cf59ec3ca5650c6517 (patch) | |
| tree | dc90291aed57d5109bdf520da26e603015bf45bf /passes/cmds/splitnets.cc | |
| parent | 8f1a32064639fa17d67bda508df941c8846a0664 (diff) | |
| download | yosys-0955a603c889e3ce86ca65cf59ec3ca5650c6517.tar.gz yosys-0955a603c889e3ce86ca65cf59ec3ca5650c6517.tar.bz2 yosys-0955a603c889e3ce86ca65cf59ec3ca5650c6517.zip | |
cxxrtl: disambiguate values/wires and their aliases in debug info.
With this change, it is easier to see which signals carry state (only
wire<>s appear as `reg` in VCD files) and to construct a minimal
checkpoint (CXXRTL_WIRE debug items represent the canonical smallest
set of state required to fully reconstruct the simulation).
Diffstat (limited to 'passes/cmds/splitnets.cc')
0 files changed, 0 insertions, 0 deletions