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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /passes/cmds/splitnets.cc | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/cmds/splitnets.cc')
| -rw-r--r-- | passes/cmds/splitnets.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 7e043bcff..7572baa35 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -63,7 +63,7 @@ struct SplitnetsWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (splitmap.count(c.wire) > 0) c = splitmap.at(c.wire).at(c.offset); sig.optimize(); @@ -144,7 +144,7 @@ struct SplitnetsPass : public Pass { continue; RTLIL::SigSpec sig = p.second.optimized(); - for (auto &chunk : sig.chunks) { + for (auto &chunk : sig.__chunks) { if (chunk.wire == NULL) continue; if (chunk.wire->port_id == 0 || flag_ports) { |