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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-07-11 23:57:53 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-07-12 00:47:34 +0200 |
commit | 009940f56ca71cc8655a13a514371eb5757b96ca (patch) | |
tree | 8b194a81a92590973eb662c1207a876d010b2966 /passes/cmds | |
parent | 726fabd65e51c7a15a2a2dc24d3b99426ef43ad2 (diff) | |
download | yosys-009940f56ca71cc8655a13a514371eb5757b96ca.tar.gz yosys-009940f56ca71cc8655a13a514371eb5757b96ca.tar.bz2 yosys-009940f56ca71cc8655a13a514371eb5757b96ca.zip |
rtlil: Make Process handling more uniform with Cell and Wire.
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
to add and remove processes
Diffstat (limited to 'passes/cmds')
-rw-r--r-- | passes/cmds/bugpoint.cc | 9 | ||||
-rw-r--r-- | passes/cmds/delete.cc | 10 |
2 files changed, 8 insertions, 11 deletions
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index c782d9a38..16ac5b6a7 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -275,7 +275,7 @@ struct BugpointPass : public Pass { if (mod->get_blackbox_attribute()) continue; - RTLIL::IdString removed_process; + RTLIL::Process *removed_process = nullptr; for (auto process : mod->processes) { if (process.second->get_bool_attribute(ID::bugpoint_keep)) @@ -284,13 +284,12 @@ struct BugpointPass : public Pass { if (index++ == seed) { log_header(design, "Trying to remove process %s.%s.\n", log_id(mod), log_id(process.first)); - removed_process = process.first; + removed_process = process.second; break; } } - if (!removed_process.empty()) { - delete mod->processes[removed_process]; - mod->processes.erase(removed_process); + if (removed_process) { + mod->remove(removed_process); return design_copy; } } diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 48a2179b1..e341f29d6 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -90,7 +90,7 @@ struct DeletePass : public Pass { pool<RTLIL::Wire*> delete_wires; pool<RTLIL::Cell*> delete_cells; - pool<RTLIL::IdString> delete_procs; + pool<RTLIL::Process*> delete_procs; pool<RTLIL::IdString> delete_mems; for (auto wire : module->selected_wires()) @@ -110,7 +110,7 @@ struct DeletePass : public Pass { for (auto &it : module->processes) if (design->selected(module, it.second)) - delete_procs.insert(it.first); + delete_procs.insert(it.second); for (auto &it : delete_mems) { delete module->memories.at(it); @@ -120,10 +120,8 @@ struct DeletePass : public Pass { for (auto &it : delete_cells) module->remove(it); - for (auto &it : delete_procs) { - delete module->processes.at(it); - module->processes.erase(it); - } + for (auto &it : delete_procs) + module->remove(it); module->remove(delete_wires); |