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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-21 12:35:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-21 12:35:06 +0200 |
| commit | 1d88f1cf9f2088de7825f5292db5b40d4f73d036 (patch) | |
| tree | ef1eeba2dcddbe957dabb8147b2b81cdc0d2ecd3 /passes/cmds | |
| parent | 3cb61d03f8722fddfa14877accae1b3ca51e3926 (diff) | |
| download | yosys-1d88f1cf9f2088de7825f5292db5b40d4f73d036.tar.gz yosys-1d88f1cf9f2088de7825f5292db5b40d4f73d036.tar.bz2 yosys-1d88f1cf9f2088de7825f5292db5b40d4f73d036.zip | |
Removed deprecated module->new_wire()
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/connect.cc | 2 | ||||
| -rw-r--r-- | passes/cmds/delete.cc | 2 | ||||
| -rw-r--r-- | passes/cmds/splice.cc | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 7da2b9517..f99cb9b50 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->new_wire(sig.width, NEW_ID); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.width); for (auto &it : module->cells) for (auto &port : it.second->connections) diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 1c02752c2..ce6ac4aff 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -30,7 +30,7 @@ struct DeleteWireWorker sig.optimize(); for (auto &c : sig.chunks) if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { - c.wire = module->new_wire(c.width, NEW_ID); + c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; } } diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 6d920dbc5..a48a54a12 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -77,7 +77,7 @@ struct SpliceWorker cell->parameters["\\A_WIDTH"] = sig_a.width; cell->parameters["\\Y_WIDTH"] = sig.width; cell->connections["\\A"] = sig_a; - cell->connections["\\Y"] = module->new_wire(sig.width, NEW_ID); + cell->connections["\\Y"] = module->addWire(NEW_ID, sig.width); new_sig = cell->connections["\\Y"]; module->add(cell); } @@ -138,7 +138,7 @@ struct SpliceWorker cell->parameters["\\B_WIDTH"] = sig2.width; cell->connections["\\A"] = new_sig; cell->connections["\\B"] = sig2; - cell->connections["\\Y"] = module->new_wire(new_sig.width + sig2.width, NEW_ID); + cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.width + sig2.width); new_sig = cell->connections["\\Y"]; module->add(cell); } |