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author | Clifford Wolf <clifford@clifford.at> | 2015-01-22 21:23:01 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-01-22 21:23:01 +0100 |
commit | 1cb4c925d03de289f37a40b6eceb57ced8dce295 (patch) | |
tree | 88a08f99571ae64a4456f1b791d26b946920d55f /passes/equiv/equiv_make.cc | |
parent | 5707ba22c10048bef7d5ad81d090e3dd31d779a4 (diff) | |
download | yosys-1cb4c925d03de289f37a40b6eceb57ced8dce295.tar.gz yosys-1cb4c925d03de289f37a40b6eceb57ced8dce295.tar.bz2 yosys-1cb4c925d03de289f37a40b6eceb57ced8dce295.zip |
Improvements in equiv_make, equiv_induct
Diffstat (limited to 'passes/equiv/equiv_make.cc')
-rw-r--r-- | passes/equiv/equiv_make.cc | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 07374cfc3..be1480e94 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -176,11 +176,45 @@ struct EquivMakeWorker } } + void find_undriven_nets() + { + pool<SigBit> undriven_bits; + SigMap assign_map(equiv_mod); + + for (auto wire : equiv_mod->wires()) { + for (auto bit : assign_map(wire)) + if (bit.wire) + undriven_bits.insert(bit); + } + + for (auto wire : equiv_mod->wires()) { + if (wire->port_input) + for (auto bit : assign_map(wire)) + undriven_bits.erase(bit); + } + + for (auto cell : equiv_mod->cells()) { + for (auto &conn : cell->connections()) + if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) + for (auto bit : assign_map(conn.second)) + undriven_bits.erase(bit); + } + + SigSpec undriven_sig(undriven_bits); + undriven_sig.sort_and_unify(); + + for (auto chunk : undriven_sig.chunks()) { + log("Setting undriven nets to undef: %s\n", log_signal(chunk)); + equiv_mod->connect(chunk, SigSpec(State::Sx, chunk.width)); + } + } + void run() { copy_to_equiv(); find_same_wires(); find_same_cells(); + find_undriven_nets(); } }; |