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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-09 12:42:32 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-09 12:42:32 +0200 |
| commit | 05483619f0b776eda2f96ca7a9bfb8cdc3732a0e (patch) | |
| tree | df893fc9929cc54f684f9975834220743199d93e /passes/fsm/fsm_expand.cc | |
| parent | d97782b848bf5da4529e5b732b1ad06177539a93 (diff) | |
| download | yosys-05483619f0b776eda2f96ca7a9bfb8cdc3732a0e.tar.gz yosys-05483619f0b776eda2f96ca7a9bfb8cdc3732a0e.tar.bz2 yosys-05483619f0b776eda2f96ca7a9bfb8cdc3732a0e.zip | |
Some fixes to improve determinism
Diffstat (limited to 'passes/fsm/fsm_expand.cc')
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index ae1f4c166..5756b10c7 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -30,12 +30,12 @@ struct FsmExpand RTLIL::Module *module; RTLIL::Cell *fsm_cell; SigMap assign_map; - SigSet<RTLIL::Cell*> sig2driver, sig2user; + SigSet<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> sig2driver, sig2user; CellTypes ct; - std::set<RTLIL::Cell*> merged_set; - std::set<RTLIL::Cell*> current_set; - std::set<RTLIL::Cell*> no_candidate_set; + std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> merged_set; + std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> current_set; + std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> no_candidate_set; bool already_optimized; int limit_transitions; |