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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-25 02:24:11 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-25 02:24:11 +0100 |
| commit | 0f5378b5592f944a1a4c01fb75a0556b11b87cdd (patch) | |
| tree | 7c32311f8c3452c1f31962cc9131219fca22368b /passes/fsm/fsm_expand.cc | |
| parent | 4a7d624bef21ee6fd8ac68b2c87fc50f3a8214ea (diff) | |
| download | yosys-0f5378b5592f944a1a4c01fb75a0556b11b87cdd.tar.gz yosys-0f5378b5592f944a1a4c01fb75a0556b11b87cdd.tar.bz2 yosys-0f5378b5592f944a1a4c01fb75a0556b11b87cdd.zip | |
Improved method for finding fsm_expand candidates
Diffstat (limited to 'passes/fsm/fsm_expand.cc')
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 0446c113d..ae1f4c166 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -43,7 +43,8 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") - return cell->connections.at("\\A").width < 2; + if (cell->connections.at("\\A").width < 2) + return true; RTLIL::SigSpec new_signals; if (cell->connections.count("\\A") > 0) @@ -52,16 +53,18 @@ struct FsmExpand new_signals.append(assign_map(cell->connections["\\B"])); if (cell->connections.count("\\S") > 0) new_signals.append(assign_map(cell->connections["\\S"])); + if (cell->connections.count("\\Y") > 0) + new_signals.append(assign_map(cell->connections["\\Y"])); new_signals.sort_and_unify(); new_signals.remove_const(); - if (new_signals.width > 4) - return false; - new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"])); new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); + if (new_signals.width > 3) + return false; + if (cell->connections.count("\\Y") > 0) { new_signals.append(assign_map(cell->connections["\\Y"])); new_signals.sort_and_unify(); @@ -140,7 +143,6 @@ struct FsmExpand input_sig.sort_and_unify(); input_sig.remove_const(); - assert(input_sig.width <= 4 || cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux"); std::vector<RTLIL::Const> truth_tab; for (int i = 0; i < (1 << input_sig.width); i++) { |