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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /passes/fsm/fsm_expand.cc | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/fsm/fsm_expand.cc')
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 5756b10c7..e4d20077c 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -43,7 +43,7 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") - if (cell->connections.at("\\A").width < 2) + if (cell->connections.at("\\A").__width < 2) return true; RTLIL::SigSpec new_signals; @@ -62,7 +62,7 @@ struct FsmExpand new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"])); new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); - if (new_signals.width > 3) + if (new_signals.__width > 3) return false; if (cell->connections.count("\\Y") > 0) { @@ -73,7 +73,7 @@ struct FsmExpand new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); } - if (new_signals.width > 2) + if (new_signals.__width > 2) return false; return true; @@ -145,8 +145,8 @@ struct FsmExpand std::vector<RTLIL::Const> truth_tab; - for (int i = 0; i < (1 << input_sig.width); i++) { - RTLIL::Const in_val(i, input_sig.width); + for (int i = 0; i < (1 << input_sig.__width); i++) { + RTLIL::Const in_val(i, input_sig.__width); RTLIL::SigSpec A, B, S; if (cell->connections.count("\\A") > 0) A = assign_map(cell->connections["\\A"]); @@ -166,17 +166,17 @@ struct FsmExpand FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - fsm_data.num_inputs += input_sig.width; + fsm_data.num_inputs += input_sig.__width; fsm_cell->connections["\\CTRL_IN"].append(input_sig); - fsm_data.num_outputs += output_sig.width; + fsm_data.num_outputs += output_sig.__width; fsm_cell->connections["\\CTRL_OUT"].append(output_sig); std::vector<FsmData::transition_t> new_transition_table; for (auto &tr : fsm_data.transition_table) { - for (int i = 0; i < (1 << input_sig.width); i++) { + for (int i = 0; i < (1 << input_sig.__width); i++) { FsmData::transition_t new_tr = tr; - RTLIL::Const in_val(i, input_sig.width); + RTLIL::Const in_val(i, input_sig.__width); RTLIL::Const out_val = truth_tab[i]; RTLIL::SigSpec ctrl_in = new_tr.ctrl_in; RTLIL::SigSpec ctrl_out = new_tr.ctrl_out; |