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authorClifford Wolf <clifford@clifford.at>2016-04-21 23:28:37 +0200
committerClifford Wolf <clifford@clifford.at>2016-04-21 23:28:37 +0200
commit0bc95f1e049afc35bb5ea30663b0a5725dfbf584 (patch)
tree3a8641d3a9bb5794a24145ce368f3db7a3963709 /passes/fsm/fsm_extract.cc
parent1565d1af69f552b790aa43fd6be194ee59ab76f3 (diff)
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Added "yosys -D" feature
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
-rw-r--r--passes/fsm/fsm_extract.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index d61ac568d..95cb498e3 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -416,7 +416,7 @@ struct FsmExtractPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
- log_header("Executing FSM_EXTRACT pass (extracting FSM from design).\n");
+ log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
extra_args(args, 1, design);
CellTypes ct;