diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-12-04 14:14:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-04 14:14:05 +0100 |
| commit | 93a70959f3f67ffcee8159b18a5f68904e32a074 (patch) | |
| tree | 1bf68c1a36c3d126fdb396b0ea9c06bcdc2040fb /passes/fsm/fsm_map.cc | |
| parent | a2d053694b6269bab8871a810142943fac6a3a18 (diff) | |
| download | yosys-93a70959f3f67ffcee8159b18a5f68904e32a074.tar.gz yosys-93a70959f3f67ffcee8159b18a5f68904e32a074.tar.bz2 yosys-93a70959f3f67ffcee8159b18a5f68904e32a074.zip | |
Replaced RTLIL::Const::str with generic decoder method
Diffstat (limited to 'passes/fsm/fsm_map.cc')
| -rw-r--r-- | passes/fsm/fsm_map.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index b8edf420a..c30cf1fe7 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -168,7 +168,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // create state register RTLIL::Wire *state_wire = new RTLIL::Wire; - state_wire->name = fsm_cell->parameters["\\NAME"].str; + state_wire->name = fsm_cell->parameters["\\NAME"].decode_string(); while (module->count_id(state_wire->name) > 0) state_wire->name += "_"; state_wire->width = fsm_data.state_bits; |