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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-10 09:52:14 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-10 09:52:14 +0200 |
| commit | f54bf1631ff37a83733c162e6ebd188c1d5ea18f (patch) | |
| tree | 21d24c49c50f17a53a9bc8fe4118752ff845e55d /passes/fsm/fsm_map.cc | |
| parent | 4f812131653ebea06e3d1c3e7599492992edb771 (diff) | |
| parent | 6d77236f3845cd8785e7bdd4da3c5ef966be6043 (diff) | |
| download | yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.tar.gz yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.tar.bz2 yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.zip | |
Merge pull request #1258 from YosysHQ/eddie/cleanup
Cleanup a few barnacles across codebase
Diffstat (limited to 'passes/fsm/fsm_map.cc')
| -rw-r--r-- | passes/fsm/fsm_map.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 90c958912..80913fda8 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -133,7 +133,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const cases_vector.append(and_sig); break; case 0: - cases_vector.append(RTLIL::SigSpec(1, 1)); + cases_vector.append(State::S1); break; default: log_abort(); @@ -150,7 +150,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const } else if (cases_vector.size() == 1) { module->connect(RTLIL::SigSig(output, cases_vector)); } else { - module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); + module->connect(RTLIL::SigSig(output, State::S0)); } } |