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| author | Clifford Wolf <clifford@clifford.at> | 2014-03-11 11:39:30 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-03-11 11:39:30 +0100 |
| commit | 4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c (patch) | |
| tree | 05b0aa06aceb945e209adc497ca8c18174955747 /passes/fsm/fsm_recode.cc | |
| parent | 78c64a64017dbc3e15aeac3246d5fc159555fbe2 (diff) | |
| download | yosys-4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c.tar.gz yosys-4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c.tar.bz2 yosys-4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c.zip | |
Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
Diffstat (limited to 'passes/fsm/fsm_recode.cc')
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