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author | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
commit | 207736b4ee0363ff6714071e64024965916eafc2 (patch) | |
tree | 31092cfab4323500bc491d8b59deee9e297730d0 /passes/fsm/fsmdata.h | |
parent | da923c198e770806a4abb749acc75fa337247920 (diff) | |
download | yosys-207736b4ee0363ff6714071e64024965916eafc2.tar.gz yosys-207736b4ee0363ff6714071e64024965916eafc2.tar.bz2 yosys-207736b4ee0363ff6714071e64024965916eafc2.zip |
Import more std:: stuff into Yosys namespace
Diffstat (limited to 'passes/fsm/fsmdata.h')
-rw-r--r-- | passes/fsm/fsmdata.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 1b98ccbac..68222769a 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -39,7 +39,7 @@ struct FsmData int state_num_log2 = 0; for (int i = state_table.size(); i > 0; i = i >> 1) state_num_log2++; - state_num_log2 = std::max(state_num_log2, 1); + state_num_log2 = max(state_num_log2, 1); cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits); cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size()); |