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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /passes/fsm/fsmdata.h | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/fsm/fsmdata.h')
| -rw-r--r-- | passes/fsm/fsmdata.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 225f34a9d..6b1753060 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -143,15 +143,15 @@ struct FsmData log(" Input signals:\n"); RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"]; sig_in.expand(); - for (size_t i = 0; i < sig_in.chunks.size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_in.chunks[i])); + for (size_t i = 0; i < sig_in.__chunks.size(); i++) + log(" %3zd: %s\n", i, log_signal(sig_in.__chunks[i])); log("\n"); log(" Output signals:\n"); RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"]; sig_out.expand(); - for (size_t i = 0; i < sig_out.chunks.size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_out.chunks[i])); + for (size_t i = 0; i < sig_out.__chunks.size(); i++) + log(" %3zd: %s\n", i, log_signal(sig_out.__chunks[i])); log("\n"); log(" State encoding:\n"); |