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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-04-08 20:54:31 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-04-12 15:11:09 +0200 |
| commit | 2021ddecb39d3848e180cd7e078facf82132440f (patch) | |
| tree | a768dd33906dae73482f79cd78c8bce8ddd56f0d /passes/fsm | |
| parent | 41d4e91f388f41c97f71567cd5a0f5652a5968fd (diff) | |
| download | yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.gz yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.bz2 yosys-2021ddecb39d3848e180cd7e078facf82132440f.zip | |
Squelch trailing whitespace
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 6a560f166..9fb5446e7 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -180,7 +180,7 @@ static void detect_fsm(RTLIL::Wire *wire) for (auto &port_it : cell->connections()) if (cell->output(port_it.first)) { SigSpec sig = assign_map(port_it.second); - Const val(set_output ? State::S1 : State::S0, GetSize(sig)); + Const val(set_output ? State::S1 : State::S0, GetSize(sig)); ce.set(sig, val); } } @@ -215,7 +215,7 @@ static void detect_fsm(RTLIL::Wire *wire) for (auto w : warnings) warnmsg += " " + w; log_warning("%s", warnmsg.c_str()); } else { - log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire)); + log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire)); } } else |