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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-03 18:42:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-03 18:42:36 +0200 |
| commit | 766dd514472e189dde04363c1ee715be7b8a917e (patch) | |
| tree | dd6a86fc15cb212e0b8dd714b429416024ca6b6e /passes/fsm | |
| parent | f0c9a099d20bc3ddee55155fe3d37b8d8d189a01 (diff) | |
| download | yosys-766dd514472e189dde04363c1ee715be7b8a917e.tar.gz yosys-766dd514472e189dde04363c1ee715be7b8a917e.tar.bz2 yosys-766dd514472e189dde04363c1ee715be7b8a917e.zip | |
Bugfix in fsm_extract
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 7d68999fc..d61ac568d 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -56,6 +56,17 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL std::set<sig2driver_entry_t> cellport_list; sig2driver.find(sig, cellport_list); + + if (GetSize(cellport_list) > 1) { + log(" found %d combined drivers for state signal %s.\n", GetSize(cellport_list), log_signal(sig)); + return false; + } + + if (GetSize(cellport_list) < 1) { + log(" found no driver for state signal %s.\n", log_signal(sig)); + return false; + } + for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); @@ -90,9 +101,11 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state)); } while (0); - if (ctrl.extract(sig_s).size() == 0) { - log(" found ctrl input: %s\n", log_signal(sig_s)); - ctrl.append(sig_s); + for (auto sig_s_bit : sig_s) { + if (ctrl.extract(sig_s_bit).empty()) { + log(" found ctrl input: %s\n", log_signal(sig_s_bit)); + ctrl.append(sig_s_bit); + } } if (!find_states(sig_aa, dff_out, ctrl, states)) |