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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-02-08 22:12:29 -0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-02-08 22:12:29 -0800 |
| commit | 0d7e71f7abd49d1c95f0657993b55bb5f66317a1 (patch) | |
| tree | b2f77c79c6335d9b2b9dde1938f445c48ba00164 /passes/hierarchy/hierarchy.cc | |
| parent | 0c83a30f950d766ddd09bb744ee93e2433095b5c (diff) | |
| parent | ef4a28e112be10d3d62395f68e53e8b7e42dbf68 (diff) | |
| download | yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.tar.gz yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.tar.bz2 yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 337af7fd7..4786aacaf 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -175,16 +175,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check { filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v"; if (check_file_exists(filename)) { - std::vector<std::string> args; - args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "verilog"); goto loaded_module; } filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; if (check_file_exists(filename)) { - std::vector<std::string> args; - args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "ilang"); goto loaded_module; } @@ -317,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); - if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume")) + if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$cover")) return cache[mod] = true; } return cache[mod]; |