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authorMiodrag Milanović <mmicko@gmail.com>2022-11-25 17:40:57 +0100
committerGitHub <noreply@github.com>2022-11-25 17:40:57 +0100
commit448a796e155416884c5fa45465da4e5ecc9f75a4 (patch)
tree164722d2699a98b149b740562f0f7c04a2628919 /passes/hierarchy/hierarchy.cc
parentc55c514cdbd5a7968c17689876f2ced282071f9c (diff)
parentf764cd16556b638b2857a3df9b77281c1bf872a0 (diff)
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Merge pull request #3560 from YosysHQ/verific_conf
Support importing verilog configurations using Verific
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
-rw-r--r--passes/hierarchy/hierarchy.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index eea6abb04..bf0137503 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -960,7 +960,7 @@ struct HierarchyPass : public Pass {
if (top_mod == nullptr && !load_top_mod.empty()) {
#ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending) {
- verific_import(design, parameters, load_top_mod);
+ load_top_mod = verific_import(design, parameters, load_top_mod);
top_mod = design->module(RTLIL::escape_id(load_top_mod));
}
#endif