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| author | whitequark <whitequark@whitequark.org> | 2020-08-27 11:24:06 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-27 11:24:06 +0000 |
| commit | 702f7c0253dcf9410050586a5e56da044e3277a3 (patch) | |
| tree | ab94c9121ceb78152a538843e82f69228e938dde /passes/hierarchy/hierarchy.cc | |
| parent | 880df4c89763464b471b1e2044f3f296bb3332b4 (diff) | |
| parent | 00e7dec7f54eb2e4f18112e5c0007a55287fdf8e (diff) | |
| download | yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.gz yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.bz2 yosys-702f7c0253dcf9410050586a5e56da044e3277a3.zip | |
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil
Replace "ILANG" with "RTLIL" everywhere
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a2a428d15..90b25949d 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -224,7 +224,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check { {".v", "verilog"}, {".sv", "verilog -sv"}, - {".il", "ilang"} + {".il", "rtlil"} }; for (auto &ext : extensions_list) |