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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-29 16:33:56 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-29 16:35:13 +0200 |
| commit | 77e2d39cd079ba98340f55f57e8a6462fb709442 (patch) | |
| tree | f37e97d7496fed7221f8fdbcb5e0a018fddeee50 /passes/hierarchy/hierarchy.cc | |
| parent | 03c96f9ce7120adf1c9bab93485a3b4bf6493ae9 (diff) | |
| download | yosys-77e2d39cd079ba98340f55f57e8a6462fb709442.tar.gz yosys-77e2d39cd079ba98340f55f57e8a6462fb709442.tar.bz2 yosys-77e2d39cd079ba98340f55f57e8a6462fb709442.zip | |
Allow "hierarchy -generate" for $__ cells
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index c869ec729..a1361c680 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -41,7 +41,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell for (auto i2 : i1.second->cells_) { RTLIL::Cell *cell = i2.second; - if (cell->type[0] == '$' || design->modules_.count(cell->type) > 0) + if (design->has(cell->type)) + continue; + if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__") continue; for (auto &pattern : celltypes) if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE)) |