diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-02-04 16:50:13 +0100 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-02-04 16:50:13 +0100 |
commit | 7a5f378baef95bb1507333d86143662de1b08098 (patch) | |
tree | 4e5f3a5256ba4be6d597684cc703253058e87013 /passes/hierarchy/hierarchy.cc | |
parent | 7a66b38c3e7e05e712144d63691f517ecca18d1d (diff) | |
download | yosys-7a5f378baef95bb1507333d86143662de1b08098.tar.gz yosys-7a5f378baef95bb1507333d86143662de1b08098.tar.bz2 yosys-7a5f378baef95bb1507333d86143662de1b08098.zip |
Added hierarchy -purge_lib option
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 01e287e94..50d0e6e47 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -210,7 +210,7 @@ static void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &us } } -static void hierarchy(RTLIL::Design *design, RTLIL::Module *top) +static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) { std::set<RTLIL::Module*> used; hierarchy_worker(design, used, top, 0); @@ -221,6 +221,8 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top) del_modules.push_back(it.second); for (auto mod : del_modules) { + if (!purge_lib && mod->get_bool_attribute("\\blackbox")) + continue; log("Removing unused module `%s'.\n", mod->name.c_str()); design->modules.erase(mod->name); delete mod; @@ -247,6 +249,10 @@ struct HierarchyPass : public Pass { log(" also check the design hierarchy. this generates an error when\n"); log(" an unknown module is used as cell type.\n"); log("\n"); + log(" -purge_lib\n"); + log(" by default the hierarchy command will not remove library (blackbox)\n"); + log(" module. use this options to also remove unused blackbox modules.\n"); + log("\n"); log(" -libdir <directory>\n"); log(" search for files named <module_name>.v in the specified directory\n"); log(" for unkown modules and automatically run read_verilog for each\n"); @@ -286,6 +292,7 @@ struct HierarchyPass : public Pass { log_header("Executing HIERARCHY pass (managing design hierarchy).\n"); bool flag_check = false; + bool purge_lib = false; RTLIL::Module *top_mod = NULL; std::vector<std::string> libdirs; @@ -340,6 +347,10 @@ struct HierarchyPass : public Pass { flag_check = true; continue; } + if (args[argidx] == "-purge_lib") { + purge_lib = true; + continue; + } if (args[argidx] == "-keep_positionals") { keep_positionals = true; continue; @@ -376,7 +387,7 @@ struct HierarchyPass : public Pass { top_mod = mod_it.second; if (top_mod != NULL) - hierarchy(design, top_mod); + hierarchy(design, top_mod, purge_lib); bool did_something = true; bool did_something_once = false; @@ -398,7 +409,7 @@ struct HierarchyPass : public Pass { if (top_mod != NULL && did_something_once) { log_header("Re-running hierarchy analysis..\n"); - hierarchy(design, top_mod); + hierarchy(design, top_mod, purge_lib); } if (top_mod != NULL) { |