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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 09:00:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 09:00:06 -0700 |
| commit | 8fe0a961b306ef0c9c5de912833c6d92aed5f363 (patch) | |
| tree | 10325fb4b9a5d9a481177f0360fdbb8026e66367 /passes/hierarchy/hierarchy.cc | |
| parent | a20ed260e1b12da64bc4b40682c53145f6ffe827 (diff) | |
| parent | f4abc21d8ad79621cc24852bd76abf40a9d9f702 (diff) | |
| download | yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.tar.gz yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.tar.bz2 yosys-8fe0a961b306ef0c9c5de912833c6d92aed5f363.zip | |
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 88c339e8c..b8ff99884 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -346,9 +346,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check } RTLIL::Module *mod = design->modules_[cell->type]; - if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) { + if (design->modules_.at(cell->type)->get_blackbox_attribute()) { if (flag_simcheck) - log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox module.\n", + log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox/whitebox module.\n", cell->type.c_str(), module->name.c_str(), cell->name.c_str()); continue; } @@ -451,7 +451,7 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString:: if (indent == 0) log("Top module: %s\n", mod->name.c_str()); - else if (!mod->get_bool_attribute("\\blackbox")) + else if (!mod->get_blackbox_attribute()) log("Used module: %*s%s\n", indent, "", mod->name.c_str()); used.insert(mod); @@ -491,7 +491,7 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) int del_counter = 0; for (auto mod : del_modules) { - if (!purge_lib && mod->get_bool_attribute("\\blackbox")) + if (!purge_lib && mod->get_blackbox_attribute()) continue; log("Removing unused module `%s'.\n", mod->name.c_str()); design->modules_.erase(mod->name); @@ -910,7 +910,7 @@ struct HierarchyPass : public Pass { if (m == nullptr) continue; - if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { + if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { IdString new_m_name = m->derive(design, cell->parameters, true); if (new_m_name.empty()) continue; |