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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 20:12:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 20:12:50 +0200 |
| commit | 946ddff9cef3ea0b4dad8664319fb13074133775 (patch) | |
| tree | e35f5ebe3cd76a8e10fe945872e32c2ed3a7d815 /passes/hierarchy/hierarchy.cc | |
| parent | d49dec1f861ce11a87c48cc21c8edc1755802a5f (diff) | |
| download | yosys-946ddff9cef3ea0b4dad8664319fb13074133775.tar.gz yosys-946ddff9cef3ea0b4dad8664319fb13074133775.tar.bz2 yosys-946ddff9cef3ea0b4dad8664319fb13074133775.zip | |
Changed a lot of code to the new RTLIL::Wire constructors
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 76b667b86..8c09d2eaa 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -118,13 +118,10 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell design->modules[mod->name] = mod; for (auto &decl : ports) { - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = decl.portname; - wire->width = portwidths.at(decl.portname); + RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname)); wire->port_id = decl.index; wire->port_input = decl.input; wire->port_output = decl.output; - mod->add(wire); } for (auto ¶ : parameters) |