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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:37:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:37:54 +0200 |
| commit | e679a5d04633e0c0626057ed2760ddb9595eea5d (patch) | |
| tree | cce75cbef78ff294cc26a992347fe16b713db996 /passes/hierarchy/hierarchy.cc | |
| parent | e9dede01ca8834ea3c211862a5d6c0119b2b578a (diff) | |
| download | yosys-e679a5d04633e0c0626057ed2760ddb9595eea5d.tar.gz yosys-e679a5d04633e0c0626057ed2760ddb9595eea5d.tar.bz2 yosys-e679a5d04633e0c0626057ed2760ddb9595eea5d.zip | |
Fixed handling of boolean attributes (passes)
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index e10ea4cf6..7d712d5e4 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -113,7 +113,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; - mod->attributes["\\placeholder"] = RTLIL::Const(0, 0); + mod->attributes["\\placeholder"] = RTLIL::Const(1); design->modules[mod->name] = mod; for (auto &decl : ports) { @@ -147,7 +147,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla } if (cell->parameters.size() == 0) continue; - if (design->modules.at(cell->type)->attributes.count("\\placeholder") > 0) + if (design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) continue; RTLIL::Module *mod = design->modules[cell->type]; cell->type = mod->derive(design, cell->parameters); |