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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-28 12:57:36 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-28 12:57:36 -0800 |
| commit | b3a66dff7cac8ee98a9b26463e8858a38ea57f83 (patch) | |
| tree | b5e9335668fd02c912be638e806990345426b2fe /passes/hierarchy/submod.cc | |
| parent | 130d3b9639148fa8191937313a3ad21a7827df18 (diff) | |
| download | yosys-b3a66dff7cac8ee98a9b26463e8858a38ea57f83.tar.gz yosys-b3a66dff7cac8ee98a9b26463e8858a38ea57f83.tar.bz2 yosys-b3a66dff7cac8ee98a9b26463e8858a38ea57f83.zip | |
Move \init signal for non-port signals as long as internally driven
Diffstat (limited to 'passes/hierarchy/submod.cc')
| -rw-r--r-- | passes/hierarchy/submod.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 839f8561c..211f96175 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -175,7 +175,7 @@ struct SubmodWorker new_wire->port_output = new_wire_port_output; new_wire->start_offset = wire->start_offset; new_wire->attributes = wire->attributes; - if (new_wire->port_output) { + if (!flags.is_int_driven.is_fully_zero()) { new_wire->attributes.erase(ID(init)); auto sig = sigmap(wire); for (int i = 0; i < GetSize(sig); i++) { |