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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 15:36:09 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 15:36:09 +0200 |
| commit | 4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece (patch) | |
| tree | 917ce7eece77475cfc632f3d41f5fb8aadef64d2 /passes/hierarchy | |
| parent | 85db102e13bbd6decda3f99ef640d0991ee24b33 (diff) | |
| download | yosys-4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece.tar.gz yosys-4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece.tar.bz2 yosys-4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece.zip | |
Fixed all users of SigSpec::chunks_rw() and removed it
Diffstat (limited to 'passes/hierarchy')
| -rw-r--r-- | passes/hierarchy/submod.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index b983a840e..257301880 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -164,10 +164,10 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new RTLIL::Cell(*cell); for (auto &conn : new_cell->connections) - for (auto &c : conn.second.chunks_rw()) - if (c.wire != NULL) { - assert(wire_flags.count(c.wire) > 0); - c.wire = wire_flags[c.wire].new_wire; + for (auto &bit : conn.second) + if (bit.wire != NULL) { + assert(wire_flags.count(bit.wire) > 0); + bit.wire = wire_flags[bit.wire].new_wire; } log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); new_mod->cells[new_cell->name] = new_cell; |