Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

2 files changed, 163 insertions, 108 deletions

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 50d0e6e47..14bf8d1bd 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -28,20 +28,22 @@
 namespace {
 	struct generate_port_decl_t {
 		bool input, output;
-		std::string portname;
+		RTLIL::IdString portname;
 		int index;
 	};
 }
 
 static void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, const std::vector<generate_port_decl_t> &portdecls)
 {
-	std::set<std::string> found_celltypes;
+	std::set<RTLIL::IdString> found_celltypes;
 
-	for (auto i1 : design->modules)
-	for (auto i2 : i1.second->cells)
+	for (auto i1 : design->modules_)
+	for (auto i2 : i1.second->cells_)
 	{
 		RTLIL::Cell *cell = i2.second;
-		if (cell->type[0] == '$' || design->modules.count(cell->type) > 0)
+		if (design->has(cell->type))
+			continue;
+		if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__")
 			continue;
 		for (auto &pattern : celltypes)
 			if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE))
@@ -50,18 +52,18 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 
 	for (auto &celltype : found_celltypes)
 	{
-		std::set<std::string> portnames;
-		std::set<std::string> parameters;
-		std::map<std::string, int> portwidths;
+		std::set<RTLIL::IdString> portnames;
+		std::set<RTLIL::IdString> parameters;
+		std::map<RTLIL::IdString, int> portwidths;
 		log("Generate module for cell type %s:\n", celltype.c_str());
 
-		for (auto i1 : design->modules)
-		for (auto i2 : i1.second->cells)
+		for (auto i1 : design->modules_)
+		for (auto i2 : i1.second->cells_)
 			if (i2.second->type == celltype) {
-				for (auto &conn : i2.second->connections) {
+				for (auto &conn : i2.second->connections()) {
 					if (conn.first[0] != '$')
 						portnames.insert(conn.first);
-					portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width);
+					portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size());
 				}
 				for (auto &para : i2.second->parameters)
 					parameters.insert(para.first);
@@ -92,13 +94,13 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			}
 
 		while (portnames.size() > 0) {
-			std::string portname = *portnames.begin();
+			RTLIL::IdString portname = *portnames.begin();
 			for (auto &decl : portdecls)
 				if (decl.index == 0 && !fnmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str(), FNM_NOESCAPE)) {
 					generate_port_decl_t d = decl;
 					d.portname = portname;
 					d.index = *indices.begin();
-					assert(!indices.empty());
+					log_assert(!indices.empty());
 					indices.erase(d.index);
 					ports[d.index-1] = d;
 					portwidths[d.portname] = std::max(portwidths[d.portname], 1);
@@ -110,23 +112,22 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			portnames.erase(portname);
 		}
 
-		assert(indices.empty());
+		log_assert(indices.empty());
 
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
 		mod->attributes["\\blackbox"] = RTLIL::Const(1);
-		design->modules[mod->name] = mod;
+		design->add(mod);
 
 		for (auto &decl : ports) {
-			RTLIL::Wire *wire = new RTLIL::Wire;
-			wire->name = decl.portname;
-			wire->width = portwidths.at(decl.portname);
+			RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));
 			wire->port_id = decl.index;
 			wire->port_input = decl.input;
 			wire->port_output = decl.output;
-			mod->add(wire);
 		}
 
+		mod->fixup_ports();
+
 		for (auto &para : parameters)
 			log("  ignoring parameter %s.\n", RTLIL::id2cstr(para));
 
@@ -137,14 +138,33 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, std::vector<std::string> &libdirs)
 {
 	bool did_something = false;
+	std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
 	std::string filename;
 
-	for (auto &cell_it : module->cells)
+	for (auto &cell_it : module->cells_)
 	{
 		RTLIL::Cell *cell = cell_it.second;
 
-		if (design->modules.count(cell->type) == 0)
+		if (cell->type.substr(0, 7) == "$array:") {
+			int pos_idx = cell->type.str().find_first_of(':');
+			int pos_num = cell->type.str().find_first_of(':', pos_idx + 1);
+			int pos_type = cell->type.str().find_first_of(':', pos_num + 1);
+			int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str());
+			int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str());
+			array_cells[cell] = std::pair<int, int>(idx, num);
+			cell->type = cell->type.str().substr(pos_type + 1);
+		}
+
+		if (design->modules_.count(cell->type) == 0)
 		{
+			if (design->modules_.count("$abstract" + cell->type.str()))
+			{
+				cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters);
+				cell->parameters.clear();
+				did_something = true;
+				continue;
+			}
+
 			if (cell->type[0] == '$')
 				continue;
 
@@ -173,7 +193,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 			continue;
 
 		loaded_module:
-			if (design->modules.count(cell->type) == 0)
+			if (design->modules_.count(cell->type) == 0)
 				log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str());
 			did_something = true;
 		}
@@ -181,15 +201,47 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 		if (cell->parameters.size() == 0)
 			continue;
 
-		if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox"))
+		if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox"))
 			continue;
 
-		RTLIL::Module *mod = design->modules[cell->type];
+		RTLIL::Module *mod = design->modules_[cell->type];
 		cell->type = mod->derive(design, cell->parameters);
 		cell->parameters.clear();
 		did_something = true;
 	}
 
+	for (auto &it : array_cells)
+	{
+		RTLIL::Cell *cell = it.first;
+		int idx = it.second.first, num = it.second.second;
+
+		if (design->modules_.count(cell->type) == 0)
+			log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
+
+		RTLIL::Module *mod = design->modules_[cell->type];
+
+		for (auto &conn : cell->connections_) {
+			int conn_size = conn.second.size();
+			RTLIL::IdString portname = conn.first;
+			if (portname.substr(0, 1) == "$") {
+				int port_id = atoi(portname.substr(1).c_str());
+				for (auto &wire_it : mod->wires_)
+					if (wire_it.second->port_id == port_id) {
+						portname = wire_it.first;
+						break;
+					}
+			}
+			if (mod->wires_.count(portname) == 0)
+				log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
+			int port_size = mod->wires_.at(portname)->width;
+			if (conn_size == port_size)
+				continue;
+			if (conn_size != port_size*num)
+				log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
+			conn.second = conn.second.extract(port_size*idx, port_size);
+		}
+	}
+
 	return did_something;
 }
 
@@ -204,27 +256,29 @@ static void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &us
 		log("Used module: %*s%s\n", indent, "", mod->name.c_str());
 	used.insert(mod);
 
-	for (auto &it : mod->cells) {
-		if (design->modules.count(it.second->type) > 0)
-			hierarchy_worker(design, used, design->modules[it.second->type], indent+4);
+	for (auto &it : mod->cells_) {
+		if (design->modules_.count(it.second->type) > 0)
+			hierarchy_worker(design, used, design->modules_[it.second->type], indent+4);
 	}
 }
 
-static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
+static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool first_pass)
 {
 	std::set<RTLIL::Module*> used;
 	hierarchy_worker(design, used, top, 0);
 
 	std::vector<RTLIL::Module*> del_modules;
-	for (auto &it : design->modules)
+	for (auto &it : design->modules_)
 		if (used.count(it.second) == 0)
 			del_modules.push_back(it.second);
 
 	for (auto mod : del_modules) {
+		if (first_pass && mod->name.substr(0, 9) == "$abstract")
+			continue;
 		if (!purge_lib && mod->get_bool_attribute("\\blackbox"))
 			continue;
 		log("Removing unused module `%s'.\n", mod->name.c_str());
-		design->modules.erase(mod->name);
+		design->modules_.erase(mod->name);
 		delete mod;
 	}
 
@@ -240,7 +294,7 @@ struct HierarchyPass : public Pass {
 		log("    hierarchy [-check] [-top <module>]\n");
 		log("    hierarchy -generate <cell-types> <port-decls>\n");
 		log("\n");
-		log("In parametric designs, a module might exists in serveral variations with\n");
+		log("In parametric designs, a module might exists in several variations with\n");
 		log("different parameter values. This pass looks at all modules in the current\n");
 		log("design an re-runs the language frontends for the parametric modules as\n");
 		log("needed.\n");
@@ -255,7 +309,7 @@ struct HierarchyPass : public Pass {
 		log("\n");
 		log("    -libdir <directory>\n");
 		log("        search for files named <module_name>.v in the specified directory\n");
-		log("        for unkown modules and automatically run read_verilog for each\n");
+		log("        for unknown modules and automatically run read_verilog for each\n");
 		log("        unknown module.\n");
 		log("\n");
 		log("    -keep_positionals\n");
@@ -362,10 +416,12 @@ struct HierarchyPass : public Pass {
 			if (args[argidx] == "-top") {
 				if (++argidx >= args.size())
 					log_cmd_error("Option -top requires an additional argument!\n");
-				if (args[argidx][0] != '$' && args[argidx][0] != '\\')
-					top_mod = design->modules.count("\\" + args[argidx]) > 0 ? design->modules["\\" + args[argidx]] : NULL;
-				else
-					top_mod = design->modules.count(args[argidx]) > 0 ? design->modules[args[argidx]] : NULL;
+				top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
+				if (top_mod == NULL && design->modules_.count("$abstract" + RTLIL::escape_id(args[argidx]))) {
+					std::map<RTLIL::IdString, RTLIL::Const> empty_parameters;
+					design->modules_.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters);
+					top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
+				}
 				if (top_mod == NULL)
 					log_cmd_error("Module `%s' not found!\n", args[argidx].c_str());
 				continue;
@@ -382,25 +438,25 @@ struct HierarchyPass : public Pass {
 		log_push();
 
 		if (top_mod == NULL)
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
 					top_mod = mod_it.second;
 
 		if (top_mod != NULL)
-			hierarchy(design, top_mod, purge_lib);
+			hierarchy(design, top_mod, purge_lib, true);
 
 		bool did_something = true;
 		bool did_something_once = false;
 		while (did_something) {
 			did_something = false;
-			std::vector<std::string> modnames;
-			modnames.reserve(design->modules.size());
-			for (auto &mod_it : design->modules)
+			std::vector<RTLIL::IdString> modnames;
+			modnames.reserve(design->modules_.size());
+			for (auto &mod_it : design->modules_)
 				modnames.push_back(mod_it.first);
 			for (auto &modname : modnames) {
-				if (design->modules.count(modname) == 0)
+				if (design->modules_.count(modname) == 0)
 					continue;
-				if (expand_module(design, design->modules[modname], flag_check, libdirs))
+				if (expand_module(design, design->modules_[modname], flag_check, libdirs))
 					did_something = true;
 			}
 			if (did_something)
@@ -409,11 +465,11 @@ struct HierarchyPass : public Pass {
 
 		if (top_mod != NULL && did_something_once) {
 			log_header("Re-running hierarchy analysis..\n");
-			hierarchy(design, top_mod, purge_lib);
+			hierarchy(design, top_mod, purge_lib, false);
 		}
 
 		if (top_mod != NULL) {
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 				if (mod_it.second == top_mod)
 					mod_it.second->attributes["\\top"] = RTLIL::Const(1);
 				else
@@ -426,21 +482,21 @@ struct HierarchyPass : public Pass {
 			std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map;
 			std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
 
-			for (auto &mod_it : design->modules)
-			for (auto &cell_it : mod_it.second->cells) {
+			for (auto &mod_it : design->modules_)
+			for (auto &cell_it : mod_it.second->cells_) {
 				RTLIL::Cell *cell = cell_it.second;
-				if (design->modules.count(cell->type) == 0)
+				if (design->modules_.count(cell->type) == 0)
 					continue;
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections())
 					if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
-						pos_mods.insert(design->modules.at(cell->type));
+						pos_mods.insert(design->modules_.at(cell->type));
 						pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
 						break;
 					}
 			}
 
 			for (auto module : pos_mods)
-			for (auto &wire_it : module->wires) {
+			for (auto &wire_it : module->wires_) {
 				RTLIL::Wire *wire = wire_it.second;
 				if (wire->port_id > 0)
 					pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;
@@ -452,10 +508,10 @@ struct HierarchyPass : public Pass {
 				log("Mapping positional arguments of cell %s.%s (%s).\n",
 						RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 				std::map<RTLIL::IdString, RTLIL::SigSpec> new_connections;
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections())
 					if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 						int id = atoi(conn.first.c_str()+1);
-						std::pair<RTLIL::Module*,int> key(design->modules.at(cell->type), id);
+						std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id);
 						if (pos_map.count(key) == 0) {
 							log("  Failed to map positional argument %d of cell %s.%s (%s).\n",
 									id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
@@ -464,7 +520,7 @@ struct HierarchyPass : public Pass {
 							new_connections[pos_map.at(key)] = conn.second;
 					} else
 						new_connections[conn.first] = conn.second;
-				cell->connections = new_connections;
+				cell->connections_ = new_connections;
 			}
 		}
 
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 7d0811254..1b03ab555 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -65,9 +65,9 @@ struct SubmodWorker
 		flag_found_something = true;
 	}
 
-	void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
+	void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
 	{
-		for (auto &c : sig.chunks)
+		for (auto &c : sig.chunks())
 			if (c.wire != NULL)
 				flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
 	}
@@ -79,24 +79,24 @@ struct SubmodWorker
 		wire_flags.clear();
 		for (RTLIL::Cell *cell : submod.cells) {
 			if (ct.cell_known(cell->type)) {
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections())
 					flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
 			} else {
 				log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections())
 					flag_signal(conn.second, true, true, true, false, false);
 			}
 		}
-		for (auto &it : module->cells) {
+		for (auto &it : module->cells_) {
 			RTLIL::Cell *cell = it.second;
 			if (submod.cells.count(cell) > 0)
 				continue;
 			if (ct.cell_known(cell->type)) {
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections())
 					flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first));
 			} else {
 				flag_found_something = false;
-				for (auto &conn : cell->connections)
+				for (auto &conn : cell->connections())
 					flag_signal(conn.second, false, false, false, true, true);
 				if (flag_found_something)
 					log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
@@ -105,10 +105,10 @@ struct SubmodWorker
 
 		RTLIL::Module *new_mod = new RTLIL::Module;
 		new_mod->name = submod.full_name;
-		design->modules[new_mod->name] = new_mod;
-		int port_counter = 1, auto_name_counter = 1;
+		design->add(new_mod);
+		int auto_name_counter = 1;
 
-		std::set<std::string> all_wire_names;
+		std::set<RTLIL::IdString> all_wire_names;
 		for (auto &it : wire_flags) {
 			all_wire_names.insert(it.first->name);
 		}
@@ -123,31 +123,34 @@ struct SubmodWorker
 			if (wire->port_output)
 				flags.is_ext_used = true;
 
-			RTLIL::Wire *new_wire = new RTLIL::Wire;
-			new_wire->name = wire->name;
-			new_wire->width = wire->width;
-			new_wire->start_offset = wire->start_offset;
-			new_wire->attributes = wire->attributes;
+			bool new_wire_port_input = false;
+			bool new_wire_port_output = false;
 
 			if (flags.is_int_driven && flags.is_ext_used)
-				new_wire->port_output = true;
+				new_wire_port_output = true;
 			if (flags.is_ext_driven && flags.is_int_used)
-				new_wire->port_input = true;
+				new_wire_port_input = true;
 
 			if (flags.is_int_driven && flags.is_ext_driven)
-				new_wire->port_input = true, new_wire->port_output = true;
-
-			if (new_wire->port_input || new_wire->port_output) {
-				new_wire->port_id = port_counter++;
-				while (new_wire->name[0] == '$') {
-					std::string new_wire_name = stringf("\\n%d", auto_name_counter++);
-					if (all_wire_names.count(new_wire_name) == 0) {
-						all_wire_names.insert(new_wire_name);
-						new_wire->name = new_wire_name;
+				new_wire_port_input = true, new_wire_port_output = true;
+
+			std::string new_wire_name = wire->name.str();
+			if (new_wire_port_input || new_wire_port_output) {
+				while (new_wire_name[0] == '$') {
+					std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
+					if (all_wire_names.count(next_wire_name) == 0) {
+						all_wire_names.insert(next_wire_name);
+						new_wire_name = next_wire_name;
 					}
 				}
 			}
 
+			RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width);
+			new_wire->port_input = new_wire_port_input;
+			new_wire->port_output = new_wire_port_output;
+			new_wire->start_offset = wire->start_offset;
+			new_wire->attributes = wire->attributes;
+
 			if (new_wire->port_input && new_wire->port_output)
 				log("  signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
 			else if (new_wire->port_input)
@@ -157,36 +160,32 @@ struct SubmodWorker
 			else
 				log("  signal %s: internal\n", wire->name.c_str());
 
-			new_mod->wires[new_wire->name] = new_wire;
 			flags.new_wire = new_wire;
 		}
 
+		new_mod->fixup_ports();
+
 		for (RTLIL::Cell *cell : submod.cells) {
-			RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
-			for (auto &conn : new_cell->connections)
-				for (auto &c : conn.second.chunks)
-					if (c.wire != NULL) {
-						assert(wire_flags.count(c.wire) > 0);
-						c.wire = wire_flags[c.wire].new_wire;
+			RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
+			for (auto &conn : new_cell->connections_)
+				for (auto &bit : conn.second)
+					if (bit.wire != NULL) {
+						log_assert(wire_flags.count(bit.wire) > 0);
+						bit.wire = wire_flags[bit.wire].new_wire;
 					}
 			log("  cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
-			new_mod->cells[new_cell->name] = new_cell;
-			module->cells.erase(cell->name);
-			delete cell;
+			module->remove(cell);
 		}
 		submod.cells.clear();
 
-		RTLIL::Cell *new_cell = new RTLIL::Cell;
-		new_cell->name = submod.full_name;
-		new_cell->type = submod.full_name;
+		RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name);
 		for (auto &it : wire_flags)
 		{
 			RTLIL::Wire *old_wire = it.first;
 			RTLIL::Wire *new_wire = it.second.new_wire;
 			if (new_wire->port_id > 0)
-				new_cell->connections[new_wire->name] = RTLIL::SigSpec(old_wire);
+				new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire));
 		}
-		module->cells[new_cell->name] = new_cell;
 	}
 
 	SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, std::string opt_name = std::string()) : design(design), module(module), opt_name(opt_name)
@@ -212,10 +211,10 @@ struct SubmodWorker
 
 		if (opt_name.empty())
 		{
-			for (auto &it : module->wires)
+			for (auto &it : module->wires_)
 				it.second->attributes.erase("\\submod");
 
-			for (auto &it : module->cells)
+			for (auto &it : module->cells_)
 			{
 				RTLIL::Cell *cell = it.second;
 				if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) {
@@ -228,8 +227,8 @@ struct SubmodWorker
 
 				if (submodules.count(submod_str) == 0) {
 					submodules[submod_str].name = submod_str;
-					submodules[submod_str].full_name = module->name + "_" + submod_str;
-					while (design->modules.count(submodules[submod_str].full_name) != 0 ||
+					submodules[submod_str].full_name = module->name.str() + "_" + submod_str;
+					while (design->modules_.count(submodules[submod_str].full_name) != 0 ||
 							module->count_id(submodules[submod_str].full_name) != 0)
 						submodules[submod_str].full_name += "_";
 				}
@@ -239,7 +238,7 @@ struct SubmodWorker
 		}
 		else
 		{
-			for (auto &it : module->cells)
+			for (auto &it : module->cells_)
 			{
 				RTLIL::Cell *cell = it.second;
 				if (!design->selected(module, cell))
@@ -306,18 +305,18 @@ struct SubmodPass : public Pass {
 			Pass::call(design, "opt_clean");
 			log_header("Continuing SUBMOD pass.\n");
 
-			std::set<std::string> handled_modules;
+			std::set<RTLIL::IdString> handled_modules;
 
 			bool did_something = true;
 			while (did_something) {
 				did_something = false;
-				std::vector<std::string> queued_modules;
-				for (auto &mod_it : design->modules)
+				std::vector<RTLIL::IdString> queued_modules;
+				for (auto &mod_it : design->modules_)
 					if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first))
 						queued_modules.push_back(mod_it.first);
 				for (auto &modname : queued_modules)
-					if (design->modules.count(modname) != 0) {
-						SubmodWorker worker(design, design->modules[modname]);
+					if (design->modules_.count(modname) != 0) {
+						SubmodWorker worker(design, design->modules_[modname]);
 						handled_modules.insert(modname);
 						did_something = true;
 					}
@@ -328,7 +327,7 @@ struct SubmodPass : public Pass {
 		else
 		{
 			RTLIL::Module *module = NULL;
-			for (auto &mod_it : design->modules) {
+			for (auto &mod_it : design->modules_) {
 				if (!design->selected_module(mod_it.first))
 					continue;
 				if (module != NULL)
@@ -338,7 +337,7 @@ struct SubmodPass : public Pass {
 			if (module == NULL)
 				log("Nothing selected -> do nothing.\n");
 			else {
-				Pass::call_newsel(design, stringf("opt_clean %s", module->name.c_str()));
+				Pass::call_on_module(design, module, "opt_clean");
 				log_header("Continuing SUBMOD pass.\n");
 				SubmodWorker worker(design, module, opt_name);
 			}