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authorwhitequark <whitequark@whitequark.org>2020-12-22 01:30:29 +0000
committerGitHub <noreply@github.com>2020-12-22 01:30:29 +0000
commitdf905709ca8bc2a92e8cef6855b53c5f032e491d (patch)
tree86f32860f7b1190054f234dc83b56b7117f93aa3 /passes/hierarchy
parentb62a892b2f0b71fd6910afe68bbba9d338579f98 (diff)
parent0d8e5d965f2585e6ed151a9e92d83ee63df6172a (diff)
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Merge pull request #2491 from zachjs/port-bind-sign
Sign extend port connections where necessary
Diffstat (limited to 'passes/hierarchy')
-rw-r--r--passes/hierarchy/hierarchy.cc8
1 files changed, 6 insertions, 2 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 225e1feae..3372687e1 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -1233,14 +1233,18 @@ struct HierarchyPass : public Pass {
{
int n = GetSize(conn.second) - GetSize(w);
if (!w->port_input && w->port_output)
- module->connect(sig.extract(GetSize(w), n), Const(0, n));
+ {
+ RTLIL::SigSpec out = sig.extract(0, GetSize(w));
+ out.extend_u0(GetSize(sig), w->is_signed);
+ module->connect(sig.extract(GetSize(w), n), out.extract(GetSize(w), n));
+ }
sig.remove(GetSize(w), n);
}
else
{
int n = GetSize(w) - GetSize(conn.second);
if (w->port_input && !w->port_output)
- sig.append(Const(0, n));
+ sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
else
sig.append(module->addWire(NEW_ID, n));
}