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authorJim Lawson <ucbjrl@berkeley.edu>2018-08-22 08:42:34 -0700
committerGitHub <noreply@github.com>2018-08-22 08:42:34 -0700
commit2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef (patch)
tree02b9412c9249cce3714972c8385d66f8093bfc17 /passes/memory/memory_bram.cc
parent8b92ddb9d2635c30636b17ff3d24bc09a44b8551 (diff)
parent408077769ff022f78f10ec1ffb60926361f8dc9f (diff)
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Merge pull request #1 from YosysHQ/master
merge with YosysHQ master
Diffstat (limited to 'passes/memory/memory_bram.cc')
-rw-r--r--passes/memory/memory_bram.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index a7f9cf382..e8552bbcf 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -1120,7 +1120,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
struct MemoryBramPass : public Pass {
MemoryBramPass() : Pass("memory_bram", "map memories to block rams") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1210,7 +1210,7 @@ struct MemoryBramPass : public Pass {
log("the data bits to accommodate the enable pattern of port A.\n");
log("\n");
}
- virtual void execute(vector<string> args, Design *design)
+ void execute(vector<string> args, Design *design) YS_OVERRIDE
{
rules_t rules;