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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-04 11:30:55 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2018-10-04 11:30:55 +0200 |
| commit | 5f1fea08d5e14ecaa1cf60eb865c60132a0ce3e1 (patch) | |
| tree | 0e4d9990883c1d07549426916d5c0cb6119ebb5c /passes/memory/memory_bram.cc | |
| parent | bed6c26a6e3d12750dc59d8db1cd4a909699a202 (diff) | |
| download | yosys-5f1fea08d5e14ecaa1cf60eb865c60132a0ce3e1.tar.gz yosys-5f1fea08d5e14ecaa1cf60eb865c60132a0ce3e1.tar.bz2 yosys-5f1fea08d5e14ecaa1cf60eb865c60132a0ce3e1.zip | |
Add inout ports to cells_xtra.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/memory/memory_bram.cc')
0 files changed, 0 insertions, 0 deletions