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authorEddie Hung <eddie@fpgeh.com>2019-08-20 11:57:52 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-20 11:57:52 -0700
commitd9fe4cccbf3cc03fa57b177fd13c6e900a2134f7 (patch)
treeaceb37b755f6b112e754bbdd50f0a4a6a6ee111d /passes/memory/memory_dff.cc
parent297a9802122817e143b1e4b87fd0d4e357606a72 (diff)
parent3f4886e7a3ff14578b9c6d614efd360478e5886e (diff)
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
Diffstat (limited to 'passes/memory/memory_dff.cc')
-rw-r--r--passes/memory/memory_dff.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 32b97f27a..be4b3c100 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -262,7 +262,7 @@ struct MemoryDffWorker
mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
}
- if (cell->type == "$not" || cell->type == "$_NOT_" || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
+ if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
SigSpec sig_a = cell->getPort("\\A");
SigSpec sig_y = cell->getPort("\\Y");
if (cell->type == "$not")