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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 11:32:10 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 11:32:10 -0700 |
commit | f890cfb63b71ae7b09e19c290ec70c358dcbe9cd (patch) | |
tree | ea7602c378e794b5e7448361ba2a41d2d6a49c13 /passes/memory/memory_dff.cc | |
parent | ab1d63a56595f11e10a5326bd83ce84d08badabe (diff) | |
parent | 78b30bbb1102047585d1a2eac89b1c7f5ca7344e (diff) | |
download | yosys-f890cfb63b71ae7b09e19c290ec70c358dcbe9cd.tar.gz yosys-f890cfb63b71ae7b09e19c290ec70c358dcbe9cd.tar.bz2 yosys-f890cfb63b71ae7b09e19c290ec70c358dcbe9cd.zip |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'passes/memory/memory_dff.cc')
-rw-r--r-- | passes/memory/memory_dff.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 32b97f27a..be4b3c100 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -262,7 +262,7 @@ struct MemoryDffWorker mux_cells_a[sigmap(cell->getPort("\\A"))] = cell; mux_cells_b[sigmap(cell->getPort("\\B"))] = cell; } - if (cell->type == "$not" || cell->type == "$_NOT_" || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) { + if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) { SigSpec sig_a = cell->getPort("\\A"); SigSpec sig_y = cell->getPort("\\Y"); if (cell->type == "$not") |