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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:57:57 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
commit | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (patch) | |
tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/memory/memory_dff.cc | |
parent | b7dda723022ad00c6c0089be888eab319953faa8 (diff) | |
download | yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.gz yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.bz2 yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.zip |
Manual fixes for new cell connections API
Diffstat (limited to 'passes/memory/memory_dff.cc')
-rw-r--r-- | passes/memory/memory_dff.cc | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 0513aa3d2..999c969b5 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -52,10 +52,10 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI continue; } - RTLIL::SigSpec q_norm = cell->connections()[after ? "\\D" : "\\Q"]; + RTLIL::SigSpec q_norm = cell->get(after ? "\\D" : "\\Q"); normalize_sig(module, q_norm); - RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections()[after ? "\\Q" : "\\D"]); + RTLIL::SigSpec d = q_norm.extract(bit, &cell->get(after ? "\\Q" : "\\D")); if (d.size() != 1) continue; @@ -127,8 +127,11 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$dff") - cell->get("\\Q").replace(sig, newsig); + if (cell->type == "$dff") { + RTLIL::SigSpec new_q = cell->get("\\Q"); + new_q.replace(sig, newsig); + cell->set("\\Q", new_q); + } } } |