diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 11:57:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 11:57:52 -0700 |
| commit | d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7 (patch) | |
| tree | aceb37b755f6b112e754bbdd50f0a4a6a6ee111d /passes/memory/memory_map.cc | |
| parent | 297a9802122817e143b1e4b87fd0d4e357606a72 (diff) | |
| parent | 3f4886e7a3ff14578b9c6d614efd360478e5886e (diff) | |
| download | yosys-d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7.tar.gz yosys-d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7.tar.bz2 yosys-d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7.zip | |
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
Diffstat (limited to 'passes/memory/memory_map.cc')
| -rw-r--r-- | passes/memory/memory_map.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index a0b808e56..65bccb5ef 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -301,7 +301,7 @@ struct MemoryMapWorker RTLIL::Wire *w = w_seladdr; - if (wr_bit != RTLIL::SigSpec(1, 1)) + if (wr_bit != State::S1) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); |