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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-10 09:52:14 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-10 09:52:14 +0200 |
| commit | f54bf1631ff37a83733c162e6ebd188c1d5ea18f (patch) | |
| tree | 21d24c49c50f17a53a9bc8fe4118752ff845e55d /passes/memory/memory_share.cc | |
| parent | 4f812131653ebea06e3d1c3e7599492992edb771 (diff) | |
| parent | 6d77236f3845cd8785e7bdd4da3c5ef966be6043 (diff) | |
| download | yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.tar.gz yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.tar.bz2 yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.zip | |
Merge pull request #1258 from YosysHQ/eddie/cleanup
Cleanup a few barnacles across codebase
Diffstat (limited to 'passes/memory/memory_share.cc')
| -rw-r--r-- | passes/memory/memory_share.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 172afe0cb..eb912cfd4 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -155,7 +155,7 @@ struct MemoryShareWorker { bool ignore_data_port = false; - if (cell->type == "$mux" || cell->type == "$pmux") + if (cell->type.in("$mux", "$pmux")) { std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A")); std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B")); @@ -173,7 +173,7 @@ struct MemoryShareWorker continue; } - if ((cell->type == "$memwr" || cell->type == "$memrd") && + if (cell->type.in("$memwr", "$memrd") && cell->parameters.at("\\MEMID").decode_string() == memid) ignore_data_port = true; @@ -690,7 +690,7 @@ struct MemoryShareWorker sigmap_xmux.add(cell->getPort("\\Y"), sig_a); } - if (cell->type == "$mux" || cell->type == "$pmux") + if (cell->type.in("$mux", "$pmux")) { std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); for (int i = 0; i < int(sig_y.size()); i++) |