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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
| commit | edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487 (patch) | |
| tree | 602fc633af5de89d2d6d1bda480159318f4aa91d /passes/memory | |
| parent | 48ca1ff9ef5bba939348ceeec75ad310afd9fcf8 (diff) | |
| download | yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.gz yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.bz2 yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.zip | |
Renamed extend() to extend_xx(), changed most users to extend_u0()
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_collect.cc | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 546306822..ccc196202 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -85,12 +85,12 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) RTLIL::SigSpec data = cell->getPort("\\DATA"); RTLIL::SigSpec en = cell->getPort("\\EN"); - clk.extend(1, false); - clk_enable.extend(1, false); - clk_polarity.extend(1, false); - addr.extend(addr_bits, false); - data.extend(memory->width, false); - en.extend(memory->width, false); + clk.extend_u0(1, false); + clk_enable.extend_u0(1, false); + clk_polarity.extend_u0(1, false); + addr.extend_u0(addr_bits, false); + data.extend_u0(memory->width, false); + en.extend_u0(memory->width, false); sig_wr_clk.append(clk); sig_wr_clk_enable.append(clk_enable); @@ -112,12 +112,12 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) RTLIL::SigSpec addr = cell->getPort("\\ADDR"); RTLIL::SigSpec data = cell->getPort("\\DATA"); - clk.extend(1, false); - clk_enable.extend(1, false); - clk_polarity.extend(1, false); - transparent.extend(1, false); - addr.extend(addr_bits, false); - data.extend(memory->width, false); + clk.extend_u0(1, false); + clk_enable.extend_u0(1, false); + clk_polarity.extend_u0(1, false); + transparent.extend_u0(1, false); + addr.extend_u0(addr_bits, false); + data.extend_u0(memory->width, false); sig_rd_clk.append(clk); sig_rd_clk_enable.append(clk_enable); |