namespace Yosys

6 files changed, 32 insertions, 12 deletions

diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc
index fc3095535..502e21022 100644
--- a/passes/memory/memory.cc
+++ b/passes/memory/memory.cc
@@ -22,6 +22,9 @@
 #include <stdlib.h>
 #include <stdio.h>
 
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
 struct MemoryPass : public Pass {
 	MemoryPass() : Pass("memory", "translate memories to basic cells") { }
 	virtual void help()
@@ -73,3 +76,4 @@ struct MemoryPass : public Pass {
 	}
 } MemoryPass;
  
+PRIVATE_NAMESPACE_END
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 9c670f00f..546306822 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -23,7 +23,10 @@
 #include <algorithm>
 #include <stdlib.h>
 
-static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
 {
 	if (a->type == "$memrd" && b->type == "$memrd")
 		return a->name < b->name;
@@ -32,7 +35,7 @@ static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
 	return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
 }
 
-static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
+void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 {
 	log("Collecting $memrd and $memwr for memory `%s' in module `%s':\n",
 			memory->name.c_str(), module->name.c_str());
@@ -205,3 +208,4 @@ struct MemoryCollectPass : public Pass {
 	}
 } MemoryCollectPass;
  
+PRIVATE_NAMESPACE_END
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 302ab3abf..d3cc681a2 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -22,13 +22,16 @@
 #include <stdlib.h>
 #include <sstream>
 
-static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
 {
 	for (auto &conn : module->connections())
 		sig.replace(conn.first, conn.second);
 }
 
-static bool find_sig_before_dff(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
+bool find_sig_before_dff(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
 {
 	normalize_sig(module, sig);
 
@@ -66,7 +69,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, std::vector<RTLIL::Cell*>
 	return true;
 }
 
-static void handle_wr_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
+void handle_wr_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
 {
 	log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
 
@@ -105,7 +108,7 @@ static void handle_wr_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff
 	log("no (compatible) $dff found.\n");
 }
 
-static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
+void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 {
 	normalize_sig(module, sig);
 	sig.sort_and_unify();
@@ -123,7 +126,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 		}
 }
 
-static void handle_rd_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
+void handle_rd_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
 {
 	log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
 
@@ -161,7 +164,7 @@ static void handle_rd_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff
 	log("no (compatible) $dff found.\n");
 }
 
-static void handle_module(RTLIL::Module *module, bool flag_wr_only)
+void handle_module(RTLIL::Module *module, bool flag_wr_only)
 {
 	std::vector<RTLIL::Cell*> dff_cells;
 
@@ -216,3 +219,4 @@ struct MemoryDffPass : public Pass {
 	}
 } MemoryDffPass;
  
+PRIVATE_NAMESPACE_END
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index eecb6f35d..449604c1a 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -23,6 +23,9 @@
 #include <set>
 #include <stdlib.h>
 
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
 struct MemoryMapWorker
 {
 	RTLIL::Design *design;
@@ -339,3 +342,4 @@ struct MemoryMapPass : public Pass {
 	}
 } MemoryMapPass;
  
+PRIVATE_NAMESPACE_END
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 3ae0cd2c7..f77b304b4 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -22,9 +22,10 @@
 #include "kernel/sigtools.h"
 #include "kernel/modtools.h"
 
+USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
+bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
 {
 	if (a->type == "$memrd" && b->type == "$memrd")
 		return a->name < b->name;
@@ -741,4 +742,3 @@ struct MemorySharePass : public Pass {
 } MemorySharePass;
 
 PRIVATE_NAMESPACE_END
-
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index 5a4c4eac9..e650facb4 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -23,7 +23,10 @@
 #include <algorithm>
 #include <stdlib.h>
 
-static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 {
 	log("Creating $memrd and $memwr for memory `%s' in module `%s':\n",
 			memory->name.c_str(), module->name.c_str());
@@ -76,7 +79,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 	module->remove(memory);
 }
 
-static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
+void handle_module(RTLIL::Design *design, RTLIL::Module *module)
 {
 	std::vector<RTLIL::IdString> memcells;
 	for (auto &cell_it : module->cells_)
@@ -107,3 +110,4 @@ struct MemoryUnpackPass : public Pass {
 	}
 } MemoryUnpackPass;
  
+PRIVATE_NAMESPACE_END