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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-09 21:32:16 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-15 17:16:53 +0100 |
| commit | 3af871f969f7f5bd5201bac17544559671312a6f (patch) | |
| tree | 31425736db665b093e02c90e170644f2325740a5 /passes/opt/opt_clean.cc | |
| parent | f965b3fa54eb38bf7f0246acc874087fc696f7f5 (diff) | |
| download | yosys-3af871f969f7f5bd5201bac17544559671312a6f.tar.gz yosys-3af871f969f7f5bd5201bac17544559671312a6f.tar.bz2 yosys-3af871f969f7f5bd5201bac17544559671312a6f.zip | |
opt_clean: Remove init attribute bits together with removed DFFs.
Fixes #2546.
Diffstat (limited to 'passes/opt/opt_clean.cc')
| -rw-r--r-- | passes/opt/opt_clean.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 883374cf6..c66f45308 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -21,6 +21,7 @@ #include "kernel/sigtools.h" #include "kernel/log.h" #include "kernel/celltypes.h" +#include "kernel/ffinit.h" #include <stdlib.h> #include <stdio.h> #include <set> @@ -101,6 +102,7 @@ void rmunused_module_cells(Module *module, bool verbose) pool<SigBit> used_raw_bits; dict<SigBit, pool<Cell*>> wire2driver; dict<SigBit, vector<string>> driver_driver_logs; + FfInitVals ffinit(&sigmap, module); SigMap raw_sigmap; for (auto &it : module->connections_) { @@ -193,6 +195,8 @@ void rmunused_module_cells(Module *module, bool verbose) if (verbose) log_debug(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str()); module->design->scratchpad_set_bool("opt.did_something", true); + if (RTLIL::builtin_ff_cell_types().count(cell->type)) + ffinit.remove_init(cell->getPort(ID::Q)); module->remove(cell); count_rm_cells++; } |