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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
| commit | 52355f5185fe42e28775e897f458b38a439c0ec5 (patch) | |
| tree | 83d8984e70806c9bcc8cd6d72ea81456ca76aba6 /passes/opt/opt_clean.cc | |
| parent | 6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a (diff) | |
| download | yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.gz yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.bz2 yosys-52355f5185fe42e28775e897f458b38a439c0ec5.zip | |
Use more ID::{A,B,Y,blackbox,whitebox}
Diffstat (limited to 'passes/opt/opt_clean.cc')
| -rw-r--r-- | passes/opt/opt_clean.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 1d3a85b3a..bf75c7adc 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -482,8 +482,8 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool for (auto cell : module->cells()) if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) { bool is_signed = cell->type == ID($pos) && cell->getParam(ID(A_SIGNED)).as_bool(); - RTLIL::SigSpec a = cell->getPort(ID(A)); - RTLIL::SigSpec y = cell->getPort(ID(Y)); + RTLIL::SigSpec a = cell->getPort(ID::A); + RTLIL::SigSpec y = cell->getPort(ID::Y); a.extend_u0(GetSize(y), is_signed); module->connect(y, a); delcells.push_back(cell); @@ -491,7 +491,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool for (auto cell : delcells) { if (verbose) log_debug(" removing buffer cell `%s': %s = %s\n", cell->name.c_str(), - log_signal(cell->getPort(ID(Y))), log_signal(cell->getPort(ID(A)))); + log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A))); module->remove(cell); } if (!delcells.empty()) |