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authordh73 <dh73_fpga@qq.com>2017-11-08 20:24:01 -0600
committerdh73 <dh73_fpga@qq.com>2017-11-08 20:24:01 -0600
commitcf8cc50bf51c2fa36a3189e131a7e7fe0807ae8f (patch)
tree456b6aae2215835e602851eafc3b52bb6bb6f3de /passes/opt/opt_clean.cc
parent1fc061d90c45166f87d92f76b6fae1ec517be72f (diff)
parent9ae25039fb6e28db639372d67c1b72c4170feaa3 (diff)
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Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'passes/opt/opt_clean.cc')
-rw-r--r--passes/opt/opt_clean.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index fb1851868..2d2ffa9a1 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -392,7 +392,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
}
if (verbose)
- log(" removing redundent init attribute on %s.\n", log_id(wire));
+ log(" removing redundant init attribute on %s.\n", log_id(wire));
wire->attributes.erase("\\init");
did_something = true;