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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
| commit | 369bf81a7049c96f62af084bb5007fbf45e36ab4 (patch) | |
| tree | 92071580c9bd60888ee5861d59457947a8adfde7 /passes/opt/opt_const.cc | |
| parent | ecc30255ba70910777a4586f5bd6abc818073293 (diff) | |
| download | yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.gz yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.bz2 yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.zip | |
Added support for non-const === and !== (for miter circuits)
Diffstat (limited to 'passes/opt/opt_const.cc')
| -rw-r--r-- | passes/opt/opt_const.cc | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index b7b361e95..30d85588c 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -144,7 +144,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons #endif } - if (cell->type == "$eq" || cell->type == "$ne") + if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex") { RTLIL::SigSpec a = cell->connections["\\A"]; RTLIL::SigSpec b = cell->connections["\\B"]; @@ -160,10 +160,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons assert(a.chunks.size() == b.chunks.size()); for (size_t i = 0; i < a.chunks.size(); i++) { - if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1) - continue; - if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1) - continue; + if (cell->type == "$eq" || cell->type == "$ne") { + if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1) + continue; + if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1) + continue; + } new_a.append(a.chunks[i]); new_b.append(b.chunks[i]); } |