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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-28 17:51:16 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-28 17:51:16 +0100 |
| commit | 3da46d3437f076c27cef5121f26a1fa151dde1f6 (patch) | |
| tree | 2116520ceba65cb28603ef6685b07d25bdc9a47c /passes/opt/opt_const.cc | |
| parent | 3e8e483233321d7efadbb78ba746a7797c102a3a (diff) | |
| download | yosys-3da46d3437f076c27cef5121f26a1fa151dde1f6.tar.gz yosys-3da46d3437f076c27cef5121f26a1fa151dde1f6.tar.bz2 yosys-3da46d3437f076c27cef5121f26a1fa151dde1f6.zip | |
Renamed hashmap.h to hashlib.h, some related improvements
Diffstat (limited to 'passes/opt/opt_const.cc')
| -rw-r--r-- | passes/opt/opt_const.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index f78ea6cc3..7f800bde9 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -199,7 +199,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map; TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells; - dict<RTLIL::Cell*, std::set<RTLIL::SigBit>, hash_obj_ops> cell_to_inbit; + dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit; dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell; for (auto cell : module->cells()) |