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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
| commit | 02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch) | |
| tree | af43bf9735fe47b09dbd8807c63fe451eb82aaba /passes/opt/opt_expr.cc | |
| parent | 3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff) | |
| parent | 61f37706f93042c2d1f093dd9bfa717390911eb3 (diff) | |
| download | yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.gz yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.bz2 yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.zip | |
Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 26a3ca7bc..a05db2a4f 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -155,6 +155,13 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ new_b.append_bit(it.first.second); } + if (cell->type.in("$and", "$or") && i == GRP_CONST_A) { + log(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a)); + module->connect(new_y, new_b); + module->connect(new_conn); + continue; + } + RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); c->setPort("\\A", new_a); |