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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 13:11:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 13:11:30 -0700 |
| commit | 24553326dde876b51179e092e608ce8174a44681 (patch) | |
| tree | 29af5ce1fabcef3a105f45898b411ec4188bf97f /passes/opt/opt_expr.cc | |
| parent | 0ea7eba5f13b20de28181a66181ee821820027db (diff) | |
| parent | 8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5 (diff) | |
| download | yosys-24553326dde876b51179e092e608ce8174a44681.tar.gz yosys-24553326dde876b51179e092e608ce8174a44681.tar.bz2 yosys-24553326dde876b51179e092e608ce8174a44681.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 26a3ca7bc..a05db2a4f 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -155,6 +155,13 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ new_b.append_bit(it.first.second); } + if (cell->type.in("$and", "$or") && i == GRP_CONST_A) { + log(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a)); + module->connect(new_y, new_b); + module->connect(new_conn); + continue; + } + RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); c->setPort("\\A", new_a); |