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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 12:43:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 12:43:21 -0700 |
| commit | 849e0eeab4408ed23d16abbf9d98a3603b770514 (patch) | |
| tree | a07a6cfcfd1cf5556debf9773b2eb3d4f98a34b9 /passes/opt/opt_expr.cc | |
| parent | 31f6d745528e1cfc155e65ebb11de9499c0f11e6 (diff) | |
| download | yosys-849e0eeab4408ed23d16abbf9d98a3603b770514.tar.gz yosys-849e0eeab4408ed23d16abbf9d98a3603b770514.tar.bz2 yosys-849e0eeab4408ed23d16abbf9d98a3603b770514.zip | |
Grammar
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 0ddfa5e4c..66f360f6e 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -684,7 +684,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons bool sub = (sig_ci == State::S1 && sig_bi == State::S1); // If not a subtraction, yet there is a carry or B is inverted - // then no optimisation is possible as carry is not constant + // then no optimisation is possible as carry will not be constant if (!sub && (sig_ci != State::S0 || sig_bi != State::S0)) goto next_cell; |