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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-03 15:25:46 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-03 15:25:46 +0200 |
| commit | 97423caddaafa0fbaca6f541a9c3e17f036b198b (patch) | |
| tree | cb755ac5c276f0327c3ebb55aeaf3d120fae8b59 /passes/opt/opt_expr.cc | |
| parent | d2aa123226f39fb6d076b9a0add2ad4f0e596166 (diff) | |
| parent | 42190207b4a5ae37240e58652d173c7164f025f7 (diff) | |
| download | yosys-97423caddaafa0fbaca6f541a9c3e17f036b198b.tar.gz yosys-97423caddaafa0fbaca6f541a9c3e17f036b198b.tar.bz2 yosys-97423caddaafa0fbaca6f541a9c3e17f036b198b.zip | |
Merge pull request #985 from YosysHQ/clifford/fix981
Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index b445afdc8..512ef0cbf 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -61,7 +61,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } if (wire->port_input) driven_signals.add(sigmap(wire)); - if (wire->port_output) + if (wire->port_output || wire->get_bool_attribute("\\keep")) used_signals.add(sigmap(wire)); all_signals.add(sigmap(wire)); } @@ -88,7 +88,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } } - log_debug("Setting undriven signal in %s to constant: %s = %s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(val)); + log_debug("Setting undriven signal in %s to constant: %s = %s\n", log_id(module), log_signal(sig), log_signal(val)); module->connect(sig, val); did_something = true; } @@ -104,10 +104,15 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) if (SigBit(initval[i]) == sig[i]) initval[i] = State::Sx; } - if (initval.is_fully_undef()) + if (initval.is_fully_undef()) { + log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire)); wire->attributes.erase("\\init"); - else + did_something = true; + } else if (initval != wire->attributes.at("\\init")) { + log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval)); wire->attributes["\\init"] = initval; + did_something = true; + } } } } |