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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:51:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:51:12 -0700 |
| commit | eae5a6b12c0f44230f61ed23068e7200507f9520 (patch) | |
| tree | 51fffae9b283c2310acf18b80ec814f2602ac342 /passes/opt/opt_expr.cc | |
| parent | 52355f5185fe42e28775e897f458b38a439c0ec5 (diff) | |
| download | yosys-eae5a6b12c0f44230f61ed23068e7200507f9520.tar.gz yosys-eae5a6b12c0f44230f61ed23068e7200507f9520.tar.bz2 yosys-eae5a6b12c0f44230f61ed23068e7200507f9520.zip | |
Use ID::keep more liberally too
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 85ec9a55a..f7469853b 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -61,7 +61,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } if (wire->port_input) driven_signals.add(sigmap(wire)); - if (wire->port_output || wire->get_bool_attribute(ID(keep))) + if (wire->port_output || wire->get_bool_attribute(ID::keep)) used_signals.add(sigmap(wire)); all_signals.add(sigmap(wire)); } |