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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-07-31 23:21:37 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-11 00:04:16 +0200 |
| commit | e6f3d1c225abecf736782f43af4f36526c63f4c5 (patch) | |
| tree | 5753dd1d51863623bbcb4e1ecc716171f99a6db0 /passes/opt/opt_mem_feedback.cc | |
| parent | 681a1c07e52dc82449501f4939e6312f593449bd (diff) | |
| download | yosys-e6f3d1c225abecf736782f43af4f36526c63f4c5.tar.gz yosys-e6f3d1c225abecf736782f43af4f36526c63f4c5.tar.bz2 yosys-e6f3d1c225abecf736782f43af4f36526c63f4c5.zip | |
kernel/mem: Introduce transparency masks.
Diffstat (limited to 'passes/opt/opt_mem_feedback.cc')
| -rw-r--r-- | passes/opt/opt_mem_feedback.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc index 9e04772b4..20a2a79ed 100644 --- a/passes/opt/opt_mem_feedback.cc +++ b/passes/opt/opt_mem_feedback.cc @@ -43,6 +43,7 @@ struct OptMemFeedbackWorker RTLIL::Design *design; RTLIL::Module *module; SigMap sigmap, sigmap_xmux; + FfInitVals initvals; dict<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux; dict<RTLIL::SigBit, int> sig_users_count; @@ -245,7 +246,7 @@ struct OptMemFeedbackWorker for (int i = 0; i < wrport_idx; i++) if (port.priority_mask[i]) - mem.emulate_priority(i, wrport_idx); + mem.emulate_priority(i, wrport_idx, &initvals); } for (auto &it : portbit_conds) @@ -278,6 +279,7 @@ struct OptMemFeedbackWorker this->module = module; sigmap.set(module); + initvals.set(&sigmap, module); sig_to_mux.clear(); conditions_logic_cache.clear(); |