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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 15:05:18 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 17:56:19 +0200 |
| commit | 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 (patch) | |
| tree | 991a75afe9b009486a57834fefee075ec695a28c /passes/opt/opt_muxtree.cc | |
| parent | 5826670009e1018734de49aaf1554cb8a43d09d7 (diff) | |
| download | yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.tar.gz yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.tar.bz2 yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.zip | |
Use only module->addCell() and module->remove() to create and delete cells
Diffstat (limited to 'passes/opt/opt_muxtree.cc')
| -rw-r--r-- | passes/opt/opt_muxtree.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index dfcd55126..750a9d417 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -190,8 +190,7 @@ struct OptMuxtreeWorker continue; if (live_ports.size() == 0) { - module->cells.erase(mi.cell->name); - delete mi.cell; + module->remove(mi.cell); continue; } @@ -207,8 +206,7 @@ struct OptMuxtreeWorker { RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size()); module->connections.push_back(RTLIL::SigSig(sig_y, sig_in)); - module->cells.erase(mi.cell->name); - delete mi.cell; + module->remove(mi.cell); } else { |